Sigma-Delta PWM for class-D audio and other Sigma-delta tricks

Additional Material

• Reutemann et. al. (decimation filter)

• ... and the slides presented at the conference

• Hogenauer's original CIC filter paper

• Pastre, Schmid et. al. on a sigma-delta accelerometer

• Berkhout on class-D audio

Exercise

• Exercise 11

• Exercise 11 reference solution

Matlab Exercise

• asf_ex11.zip

• Reference Solution

The target is to build a driver for the TAS5602 by Texas Instruments. This chip expects a pulse-width modulated signal with at most 400kHz base frequency. We have an FPGA with a maximum clock frequency of 50 MHz. So what we need to do is to drive the digital PWM generator with a sigma-delta bitstream.

How to proceed:

1. Understand the 8-bit (256-step) pulse width modulator (pwmstage.mdl, go_pwmstage_00.m)
2. Replace the comparator in the sigma-delta converter by a 256-step quantizer (example: sd2multibit.mdl, go_sd2multibit_00.m)
3. Combine both and optimize SNR
4. If you want, feed audio through your solution.

Learning Targets formulated in 2009

• How a MASH converter works in principle
• How a low-distortion converter works (signal bypassing the loop filter)
• How a converter with noise coupling works
• PWM stage driven by a sigma-delta bitstream

(compiled by Hanspeter Schmid)