Sigma-Delta PWM for class-D audio and other Sigma-delta tricks

Additional Material

Exercise

Matlab Exercise

The target is to build a driver for the TAS5602 by Texas Instruments. This chip expects a pulse-width modulated signal with at most 400kHz base frequency. We have an FPGA with a maximum clock frequency of 50 MHz. So what we need to do is to drive the digital PWM generator with a sigma-delta bitstream.

How to proceed:

  1. Understand the 8-bit (256-step) pulse width modulator (pwmstage.mdl, go_pwmstage_00.m)
  2. Replace the comparator in the sigma-delta converter by a 256-step quantizer (example: sd2multibit.mdl, go_sd2multibit_00.m)
  3. Combine both and optimize SNR
  4. If you want, feed audio through your solution.

Learning Targets formulated in 2009

(compiled by Hanspeter Schmid)

Sigma-Delta PWM (last edited 2017-08-29 07:01:00 by haschmid)