Sigma-Delta PWM for class-D audio and other Sigma-delta tricks
Additional Material
The Balloon (Holiday Special)
Spoiler Alert! It is better if you do not look at this before the lecture.
Exercise
Matlab Exercisde
The goal is to build a driver for the TAS5602 by Texas Instruments. This chip expects a pulse-width modulated signal with at most 400kHz base frequency. We have an FPGA with a maximum clock frequency of 50 MHz. So what we need to do is to drive the digital PWM generator with a sigma-delta bitstream.
How to proceed:
- Understand the 8-bit (256-step) pulse width modulator (pwmstage.mdl, go_pwmstage_00.m)
- Replace the comparator in the sigma-delta converter by a 256-step quantizer (example: sd2multibit.mdl, go_sd2multibit_00.m)
- Combine both and optimize SNR
- If you want, feed audio through your solution.